1. Field of the Invention
The present invention relates to an input/output device for transferring data in serial order between data processors synchronous with a clock signal.
2. Description of the Prior Art
FIG. 6 is a block diagram showing connections among data processors having conventional clock-synchronous serial input/output devices (hereinafter called "serial input/output device"). In the figure, reference numerals 1, 6 and 11 represent micro-control units (MCU) which function as data processors, and 30, 7 and 12 represent serial input/output devices provided on the respective MCUs 1, 6 and 11. Serial input/output devices 30, 7 and 12 transmit and receive data in serial order in synchronization with a clock signal. Reference numeral 3 is the transmission data output terminal of serial input/output device 30; 4, the transmission clock output terminal of serial input/output terminal 30; 8, the reception data input terminal of serial input/output device 7; 9, the reception clock input terminal of serial input/output device 7; 13, the reception data input terminal of serial input/output device 12; 14, the reception clock input terminal of serial input/output device 12; 10, the interrupt signal input terminal of MCU 6; and 15, the interrupt signal input terminal of MCU 11. Transmission data output terminal 3 of serial input/output device 30 is connected to reception data input terminal 8 of serial input/output device 7 and to reception data input terminal 13 of serial input/output device 12. Meanwhile, transmission clock output terminal 4 of serial input/output device 30 is connected to reception clock input terminal 9 of serial input/output device 7 and to reception clock input terminal 14 of serial input/output device 12.
FIG. 7 is a block diagram of the data transmission section of a conventional input/output device. In the figure, reference numeral 16 represents a transfer data storage register for storing transferred data; 18, a shifter for transferring and outputting data stored in serial order in transfer data storage register 16 serial order,; and 20, a transmission clock signal.
FIG. 8 is a block diagram of the circuit configuration of the data receiving section of a conventional serial input/output device. Reference numeral 24 indicates a shifter for receiving data in serial order; 26, a reception buffer register for storing received data; and 27, a bus wire.
The operation of the conventional input/output device will be explained hereafter. When serial data is transferred, transmission clock signal 20 of the data transmission section of serial input/output device 30 of data processor 1 is outputted from transmission clock output terminal 4, and transferred data within data storage register 16 is outputted in serial order from transmission data output terminal 3 via shifter 18 synchronously with transmission clock signal 20. Then, transmission clock signal 20 outputted from transmission clock output terminal 4 is received by reception clock input terminal 9 of serial input/output device 7 of data processor 6 and by reception clock input terminal 14 of serial input/output device 12 of data processor 11. Data transmitted from serial input/output device 30 of data processor 1 in synchronization with transmission clock signal 20 is received by reception data input terminal 8 of serial input/output device 7 of data processor 6 and by reception data input terminal 13 of serial input/output device 12 of data processor 11, thus performing data transfer. In the transmitting serial input/output device 30 of FIG. 7, data to be transmitted are stored in the transfer data storage register 16, then stored in the shifter 18 at the start of transfer, and transmitted in serial order by the shifter 18 in synchronization with the transmission clock 20.
In the receiving serial input/output devices 7 (12) of FIG. 8, the clock, and the data to be transferred in serial order, are received by reception data input terminal 8 (13) and by reception clock input terminal 9 (14) of serial input/output device 7 in synchronization with the clock received by shifter 24 for receiving data. The data received by shifter 24 is stored in reception buffer register 26.
Since the input/output device of the prior art does not have a specific transmission/reception protocol, data can be transferred only from serial input/output 30 to both of the serial input/output devices 7 and 12. If serial input/output devices 30 and 7 are provided with the same transmission/reception protocol, data transfer between these two serial input/output devices is possible. However, to provide the serial input/output devices with the protocol would cause problems such as a reduction in the length of transmission and reception data or the prohibition of transmitting specific data.
Since the conventional clock synchronous input/output device is structured as described above, when a single transmitting serial input/output device is connected to more than one receiving serial input/output device, a specific transmission/reception protocol common to both of the transmitting serial input/output devices and to the selected receiving serial input/output device is required to transfer data between these devices.